From matmul speed to one transistor switch
What the 28 October update changed. Thirteen experiments and desk reductions ran against the five open items at the foot of this page. The two that move the picture most are both in §3: the board-to-rail step is now measured instead of carried across from a per-bit ratio, and the bottom-up count has routed wires, all of the design's capacitance, a measured glitch factor and — for the first time — the lane's transport. The remainder falls from to . Two of the three reasons that count was a floor are closed; the honest caveat is that the largest row now in it is a model the card's own zeros measurement already contradicts. §5 carries each open item's new status.
Horace He's observation is that a matrix multiply runs faster on zeros than on random numbers, although it does exactly the same arithmetic. On this card it does: 15% faster in the first seconds, 33% faster once the die is hot. Nothing about the instructions changed — only how many wires inside the chip had to move. This page follows that one difference all the way down: from TFLOPS to the governor, to watts at the board, to picojoules per multiply-add, to femtojoules per flipped bit of an operand, to the toggles of individual wires, to the gates they charge, to one transistor's gate, to the electrons in it and to the thermodynamic floor underneath. Nine steps. Six of them are measured on silicon, three are modelled, and the gap that is left is shown rather than hidden.
1. The answer
Random fp32 data makes about 13.5 of the 32 bits of each operand change from one multiply-add to the next; zeros make none change. Every changed bit drives a cascade of wires through the multiplier's Wallace tree, and every wire that moves charges a capacitance. That is the whole mechanism: the card's clock governor regulates board power to a cap, random data draws more power for the same arithmetic, so the governor gives it a lower clock, and a lower clock is fewer FLOPS. The numbers below are the same difference restated at each depth.
On a cool die, in the first eight seconds, the card does on zeros against on random fp32 — faster. Once it is hot and the thermal test takes over, zeros hold 800 MHz while random data sits on the governor's 600 MHz floor, and the gap becomes . At 800 MHz the board draws on zeros and on random data. The rungs below that are each measured in their own experiment rather than divided out of it: a random multiply-add costs over idle against on zeros, and one flipped bit of an operand costs at the board. They do agree where they can be made to meet — the operand-dependent half of the per-multiply-add budget, , spread over the operand bits a random pair changes, is per bit, inside that band — but no rung here is a quotient of the one above it, and §5 shows why the per-bit prices cannot simply be added up. Underneath that bit, a bottom-up count on an open synthesis of the same RTL finds physical net toggles per random multiply-add; the gates they charge hold transistor fins per signal net; and one minimum transistor's gate takes — about electrons across the 0.517 V rail, which is times Landauer's floor at the die's own temperature.
Since 28 October the top rung is a controlled result. The governor's cap had never been moved when this page was written; §1 and §2 read the cause from the governor's own log. E69 moved it, on aifoundry2 card 0, under the firmware field manual's gates: . All-ones operands, which throw no power step at the card's own 65 W cap, throttle to . And the sustained clamp is the thermal threshold, not the power cap: the same work holds . The cause is separately switchable — lower the cap to 50 W and the clock stays at . Three of E69's six registered rules failed as written and both sustained random cells aborted on an 85 W board bound, so this closes the cap and the raised threshold, and nothing about random data under a raised threshold.
2. The chain, step by step
Each rung below carries its number, how it was obtained, where to check it, how far to trust it, and what is still missing. The ladder is to scale in orders of magnitude: of them separate one electron from one multiply-add at the board.
Nine steps from a TFLOPS gap to one transistor
Zeros run faster than random data, on the same instructions
- How
- E64: 47 runs on aifoundry2's card, fp32/fp16/int8 against zeros, ones and random data, burst and sustained, with the governor's own trace read back.
- Source
- The power limit, not the temperature limit · data
- Confidence
- measured on one card. Four ways of reading the same gap give , depending on whether you read TFLOPS or clocks.
- Open
- No GPU run of the same kind has been logged beside it, so the comparison with Horace's original A100 result is still from his numbers, not ours.
Because a controller regulates board power to a cap, and die temperature to a trip
- How
- The governor's log names which test acted at every step. Below 65 °C only the power test fires, on a running average of about of board power; at a 66 °C reading only the thermal test fires, even for zeros. A model of that controller reproduces the mean clock of runs to .
- Source
- E64, as above. The cap is the TDP the card reads back, not a fitted number.
- Confidence
- measured for the mechanism, modelled for the cap axis.
- Measured since
- The cap was moved on 28 October (E69), and the response is the predicted one: , from a table extrapolated from 65 W measurements alone. Random operands read . A second desk result, model E64-T1, adds the temperature term the power curve was missing: it takes the all-ones sustained miss . Neither closes the item — see §5.
- Open
- Three of E69's six registered rules failed as written, both sustained random cells aborted on an 85 W board bound, and E69's own control reads 25.5 MHz and 2.5 W away from E64's four days earlier at identical settings — a thermal-path change, so no cross-session comparison is tighter than that. In E64-T1 the voltage exponent and the thermal trip are jointly unidentified: the miss crosses zero at two of eight labelled pairings and is still +18.5 MHz at the least-assumption corner.
Random data draws more watts for exactly the same arithmetic
- How
- Board power from the card's own telemetry, at fixed clock, over ten operand patterns and three clock frequencies. The static part of the draw — everything that does not depend on the data — is at 600/700/800 MHz.
- Source
- E64 and E67's anchors; the chain's own refit, chain-closure.
- Confidence
- measured, and reproduced across five weeks: the zeros-to-random step at 600 MHz reads , against a 25.1 W step measured on 21 September — agreement to within 2%.
- Open
- The static term is fitted jointly over runs that include the ones this chain then predicts, so that part of the agreement is in-sample.
The gap at the board, by operand pattern and clock
Most, but not all, of that goes to the part of the chip that computes
- How
- Two routes. The rails are logged beside the board figure in E60's ladders, giving of each step; and the camera half of the Hamming ladder put 84–86% of every rung's board step on the minion rail.
- Source
- E60 · the camera ladder (E63) · E73, the camera's heat path
- Measured since
- 28 October: the rail is measured for this multiply-add rather than carried across. Q129's rail ledger reduces E38's own telemetry on two cards and gets . The whole band sits inside the 0.70–0.89 spread below, so nothing here is contradicted — 0.75 was at the bottom of what the multiply-add shows. Because the rail is bigger the step beneath it shrinks, to . The SRAM and NoC rails are withdrawn as per-MAC switching energies: their whole window delta is their own leakage rise.
- Confidence
- measured for the rail, at the launch window and corrected to the launch temperature — by correction, not by measurement. Still a range: the choice between three leakage footings is the largest single uncertainty in the step, worth 0.04 in the ratio.
- Open
- The regulators have still never been measured directly: the 0.875 pJ row above is a fit's coefficient, and splitting it from off-rail logic needs E77, which needs a governor move. One of three cards has no usable rail data at all, so the three-card ledger is a two-card ledger. And a reduction that corrects board power to a launch temperature and then applies a fixed rail ratio double-counts, because a third or more of the within-run rise is off the metered rails — 0.23 pJ on a 5.8 pJ multiply-add.
What one fp32 multiply-add costs, over idle
- How
- E38 ran the same kernel on three cards with operands held at zeros, all-ones and random, and divided the power step by the multiply-add rate. This work's independent budget at 600 MHz — built from E67's anchors and a hart ladder, not from E38 — splits that step into .
- Source
- Sparse compute (E38), registered values read at build time from the page's own data block.
- Confidence
- measured on three cards, and the two routes agree: this work's clocking and data terms are 98% and 99% of aifoundry2's registered pair, and 103% and 105% of aifoundry3's own pair on the very card that produced the ladders.
- Open
- The three cards disagree by a factor of 1.5 on the zeros term, which is the smallest and hardest to measure.
What one changed bit of an operand costs
- How
- A Hamming ladder: the same kernel, with operand words that differ from their predecessor in a designed number of bit positions, so the only thing that changes between rungs is how many bits flip. Then a scan of all 32 positions of each operand, one at a time.
- Source
- E60, the ladder · E65, 32 B-side positions · E67, 32 A-side positions · E68, the stage map
- Confidence
- measured, on three experiments, two cards and three operand designs, agreeing to about 10%. The largest single uncertainty is not the card: it is the leakage slope used to correct each run for die temperature, which moves the price by 15%.
- Measured since
- 28 October, three results. E70's ladder settles why the single-bit prices do not add, on the B side: . One saturating curve in the additive sum fits both layouts to , and the operand carry-over this chain had to choose is measured at . E72 ran the same card at 600 MHz: , so the price follows the voltage and not the clock — the clock-scaling exponent . And E71 measured the idle leakage slope on the card E65 and E67 ran on, in the temperature band they ran in: . Re-priced at it, those experiments' positions are cheaper by .
- Open
- Which bit flips matters enormously — see the chart. Three things are newly open rather than closed. The A side's shape: E70 measured its multi-bit ladder but the saturating form is rejected there — the fitted asymptote lies 28.6 standard errors below its own top rung and the increments accelerate where saturation requires decay — so no law describes it yet. The voltage exponent is bracketed . And a leakage slope is not a card constant: it rises with die temperature, so about of the gap between the two cards' published figures is the temperature band rather than the card, and a correction quoted without its band is ambiguous at the 20–30% level. One registered rule of the re-pricing failed: of 166 positions, 164 fall, one does not move and one rises.
A flipped bit costs twelve times more at the top of the mantissa than at the bottom
The one rule that does not hold. If each bit had a fixed price you could add them: 13.5 changed bits in a random operand, times the price list, would give the energy of a random word. It does not. Summed naively over both operands the price list predicts where the card draws — too much. Within one word the measured cost per flipped bit is almost flat () while the single-bit list, applied to the same masks, would predict . Something saturates. A free-exponent power law fits the ladder best (exponent , indistinguishable from linear). Answered 28 October: the experiment that separates how many bits flip from which ones ran, on aifoundry3, in 34.7 card-minutes. It is — the same number of bits in two layouts cost different amounts, which a “how many” law cannot produce. On the B side one saturating curve in the additive sum then fits fifteen rungs to . On the A side that form is rejected and its shape is open.
How many wires actually move
- How
- The same RTL — core-et's open
txfma_top— synthesised and placed on an open 7 nm cell library with Yosys and OpenROAD, then simulated at the gate level on the same operand streams, counting every net transition. A separate recount settled what the earlier RTL bench's 21,331 was counting: a simulator over-count, not physical wires. - Source
- The open netlist · the toggle recount
- Confidence
- a stand-in, simulated. It is not this chip's netlist; it is the same logic built with an open kit at a comparable node. Two independent routes to the number of physical wires agree to 14%.
- Measured since
- Both closed on 28 October. Detailed routing closes on both open netlists — 0 DRC violations, 193 s each — and the extraction found 251,162 coupling capacitors. And the glitch factor is measured by simulating the routed netlist with and without its extracted timing: the whole unit makes . The Wallace tree glitches hardest (×2.33 in energy) and the clock tree, measured, does not glitch at all. The factor is strongly activity-dependent — ×1.00 with the operands held still, ×1.23 at eight flipped bits, ×1.57 at random — so no single number transfers to a load whose activity is not random's.
- Open
- The glitch measurement is a floor on several further axes, each named in its data directory: the delays are characterised at 0.700 V while the energy is priced at the 0.517 V rail, the design still misses its timing constraint by about 2×, and 4.6% of the “timed” netlist ran at zero delay in the simulator too. A second instrument reads ×1.76 where this one reads ×1.55 on the nearest matched pair, and the 13.5% between them is not attributed. And only the switching half of the step is measured: the cells' internal energy is scaled by the signal-transition count, because the run prices no internal energy at all — a glitch on a cell input costs internal energy whether or not the output moves, and nothing here prices that. About a third of the step is that scaled half.
What one wire's toggle charges, and how little of it is transistor
- How
- Every net in the placed design joined to the capacitance the extractor gives it, split three ways: the transistor gates at its far end, the wire inside the cells, and the wire between them. The split is weighted by how often each net actually toggles in a random multiply-add.
- Source
- The transistor ledger · the cell energy table
- Confidence
- modelled, and checked two ways that agree within 5% on signal nets.
- Open
- Corrected 27 October 2026: this note said the between-cell wire has no coupling term, so the transistor share was a ceiling. It is the other way round. Detailed routing now closes, and the global-route estimate used here was never coupling-free — it runs 20–23% above the extraction — so the transistor share is a floor and the wire share a ceiling: on this split the signal-net transistor share goes from 21.7% to about 23.4% when the extracted wire is used. Closed 28 October: the design's unpriced capacitance is now priced in full, and it was not what the earlier note said it was. 39.9% of those farads were idle nets the simulation already named, 3.2% were tied constants, 4.0% were buses lost to the simulator's own renumbering, and only 4.9% were ever made by the clock tree or the timing repair — 236 of those 252 nets already priced. The whole of it is worth +0.088 pJ per multiply-add (+0.101 with the cells' internal energy), not a doubling. The same pass found a live bug in the pricing tool: it joins the extractor's net names to the simulator's without remapping a vector whose declared least-significant bit is not zero, so it charges the wrong physical bit on the overlapping indices. A private archive cross-check of the same quantities was run on 26 October 2026 and again on ;
Only a fifth of the switching energy is transistor; the rest is wire
One minimum transistor's gate, switched
- How
- SPICE on the open kit's own BSIM-CMG FinFET device cards at 0.517 V — the minion rail — integrating the current out of the supply while the gate is driven, in all four bias cases (n- and p-type, drain held low and high). The gate charge is linear in fins to 0.01%, so "per fin" is the right unit. Inside a real cell the same fin costs its driver more, because the output swings against the input: .
- Source
- One switch, in SPICE
- Confidence
- simulated on an open kit, not on this chip's devices. The four bias cases span , which is the honest width of "one transistor".
- Open
- Short-circuit current — the brief moment both halves of a gate conduct — was bracketed rather than assumed: at this rail it adds at most over a 1 ps–2 ns range of input edge, against 59% at 0.700 V. Low voltage is what makes it negligible here.
Where thermodynamics finally stops us
- How
- Charge divided by the elementary charge, at the 0.517 V rail; Landauer's kT ln 2 evaluated at the die's own temperature rather than at room temperature.
- Source
- The ledger's
the_floorblock, every rung in one table. - Confidence
- arithmetic, once the rungs above are granted. The one trap is units: a rise and a toggle differ by exactly two, and an electron count taken from a board figure is a convention, not a measurement, because board power is not delivered at the die's rail.
- Measured since
- 28 October: the step below this one is written down. A desk note follows the switch's energy into the lattice. The rung the project's own plan priced at “about 25,000 × Landauer” is sourced and stands: it is an ASAP7 INVx1's liberty input pin, 0.620 fF, worth — a floor temperature worth 6.6% on its own. What needed correcting is a word: INVx1 is a 3× cell, so if a transistor-only number is wanted beside it the repo has two, . The energy becomes , and the new claim worth carrying is where it is born: about . The wire decides how much heat a flip makes; the transistor decides where it is born — which is why the heat movies see heat follow the logic rather than the wiring.
- Open
- No measurement of this chip's thermal path below the board: every self-heating figure is an open-literature 7 nm-class value and the narrow fin's conductivity is a simulation input. Every length below about a micrometre uses a diffusive model, which under-predicts a sub-micron hot spot.
| Event | Energy | Electrons | × Landauer at 66 °C |
|---|
3. Where a random multiply-add's energy goes
The honest way to present a chain like this is to show what it fails to account for. Below is one random
fp32 multiply-add as the card pays for it, against what the bottom-up count can name. Rebuilt 28 October
2026 from seven measurements that did not exist when this page was written; the version this page carried
until then is in the same data block under waterfall.v1, and the 27 October page rebuilds
unchanged from data-2026-10-27-q128.json.
The bottom-up count now names five sixths of what reaches the rail
| One random fp32 multiply-add, over idle | 27 Oct Q128 |
28 Oct Q129 |
|---|---|---|
| at the board (E38, three cards) | 5.78 pJ | 5.78 pJ |
| at the minion rail | 4.34 pJ from E60 | 4.77 pJ measured 4.55–4.95 |
| its arithmetic, bottom up | 1.95 pJ | 2.71 pJ 2.39–3.03 |
| its transport | not counted | 1.26–1.48 pJ |
| accounted on the rail, bottom up arithmetic + transport | 1.95 pJ | 3.65–4.51 |
| the regulators' delivery loss, and logic in step with the rails a named account, not a bottom-up one | not counted | |
| not accounted, vs the board | 3.84 pJ | |
| closure vs the board, bottom-up rows only | ||
| closure vs the board, with the regulators' step counted | no such row | of the board |
Three of those rows are one row, and that matters more than their size. Three separate measurements priced the same capacitance at three stages of knowledge, and only the last is in the ledger. Extracting the routed wire moved −0.137 pJ — the wrong way, because the global-route estimate it replaced was never coupling-free and ran 20–23% above the extraction. Pricing the capacitance the simulation had never seen moved +0.101 pJ. Then the glitch measurement simulated the routed netlist against the extracted per-net table, so it prices 100% of the extracted farads and every glitch in one pass: both earlier deltas are already inside it, and adding them again would double-count. The two roads agree, which is the check worth having: . The glitch factor itself is the largest single step any of these measurements has made, .
The biggest mover is also the weakest row. The lane's transport — register files, operand bus, result path, control, on a second open netlist Q128's ledger did not contain — is , which is a third of Q128's entire gap, more than the glitch factor, the routed wire and the unpriced capacitance together. Two cautions travel with it and neither is small. It is a range, and the range is its own clock nets: survives zero operands, two thirds of that being the accumulator index sweeping through a 64-entry read mux tree, which the card performs in the same order with zero data — so no idle subtraction can contain it. Whether the clock third is inside the idle is unmeasured. And it over-prices: in the zeros stimulus one lane's transport model costs . Its register-file array is a standard-cell latch array standing in for a compiled macro, so this is a violated ceiling, and a true accounting sits below the bottom of every range here by whatever that model over-prices. E74 (28 October) measured on the card the one part of that array a zeros stimulus cannot reach — the cells' own stored bits, which do not change while the operands do not — and it bounds them at ; the minion rail arm, registered as a figure reported beside the board and never instead of it, is the only one that excludes zero, at . In per-multiply-add terms those cells are . So the cells are not where this row over-prices: the read ports, the read mux tree and the clocking are, and they are still modelled rather than measured. That is why E74 narrows this row's caveat without removing it, and why nothing from it is added to the ledger — the model already charges for the term E74 bounded.
Two things are inside already, and are not rows. The clock network is inside the arithmetic row and always was — 0.496 pJ of the multiply-add, about a third of its switching energy — and the glitch pass measured its glitch factor at exactly ×1.000. The transport's own clock nets are the one clock term that is not inside, which is why they are drawn separately — with one caveat that makes the top of that range a ceiling for a second reason: both netlists were built with their own clock-tree root for the same lane clock, and the transport's 0.223 pJ is that second root plus its gated branches, undivided. So up to a root's worth of the high end is a term the arithmetic row may already carry, independently of whether those branches are gated at idle. Leakage is not a row either: “over idle” is already a leakage-corrected quantity, because the registered reduction subtracts a slope times the window's own die rise before anything divides it. What 28 October adds is that slope's band — re-footing the whole rail ledger on three slopes gives , smaller than every other band on this page.
Two of those rows are a closure and one of them is not bottom up. Against the rail, the closure is bottom-up throughout: the arithmetic and transport rows against a measured 4.77 pJ, . Against the board there are two answers and the table gives both. The bottom-up rows alone reach of the board, against on 27 October — that is the comparison to make. Counting the measured board-to-rail step's regulator row as well reaches , but those are a named account, not a bottom-up one: no netlist priced them, a three-rail fit did. About 15 of the percentage points between 34% and the high figure are that re-categorisation rather than bottom-up progress.
What is left, and what would close it. , where 27 October had 3.84 and 2.39. Of the three reasons the bottom-up count was a floor, two are now closed: the routing and coupling one — which pointed the other way — and the coverage one, at 100% of the extracted farads on a routed design. The third stands in a narrower form: the transport netlist is itself a floor on exactly the three axes the arithmetic netlist has cleared, with no detailed route, no glitch measurement and 37% of its capacitance priced. Four things would close the rest, in the order they matter: the register-file array measured rather than modelled; a matched hart ladder (E77) to split the regulators' 0.875 pJ delivery loss from off-rail logic; a route, an SDF and a glitch measurement on the transport netlist; and whether the lane's register files are clock-gated at idle, worth 0.223 pJ. The first of those four is narrower than it was on 27 October but not closed: E74 measured the array's storage cells and bounded them, and storage is the small part — the ports, the mux tree and the clocking are what the card's zeros measurement says the model over-prices, and they are what a compiled-macro measurement would have to reach. The remainder is still not a measurement error. It is the parts of the chip this count does not yet reach — and there are fewer of them than there were.
4. Back up the ladder: predicting the speed gap from below
A chain is only worth having if it runs in both directions. Starting from board power and the governor's own cap, the model predicts the clock each pattern settles at, and therefore the TFLOPS gap it produces.
The burst gap is a real prediction and it lands. The model predicts against a measurement of , depending on which of four published readings you take — first-eight-second TFLOPS, whole-run TFLOPS, burst clocks, or mean clock after the first 1.5 s. The point estimate sits inside that spread; the model cannot tell the four readings apart. Two inputs set how sharp it can be: the cap (64 W would give 1.159, 67 W would give 1.127) and the drift of the price list between cards, which carried as a band gives .
The cap axis is measured now, not extrapolated. Both tiles above read the governor at one factory setting when this page was written. E69 moved the cap on 28 October and the extrapolated table holds: . All-ones operands throttle to ; random operands read . So the burst prediction is no longer a prediction against a single point.
The sustained gap is not a prediction at all, and saying so is the honest result. Once the thermal test takes over, zeros clamp to the top of the clock range and random data clamps to the bottom, so the predicted ratio is 800/600 = 1.333 for any cap in a window — and of the candidate caps on the record sit inside it. The measurement is the same number by the same construction. What the chain does predict here is ordinal, and it is still a real claim: random data reaches the governor's floor and zeros does not.
The one cap that is not inside.
| Pattern | Burst clock predicted · measured |
Burst TFLOPS predicted · measured |
Sustained clock predicted · measured |
Sustained TFLOPS predicted · measured |
|---|
The chain's one real miss is in that table.
Starting one rung lower — from the price of a single flipped bit rather than from measured board power — the same arithmetic gives a range for the burst gap, , because the saturation law under step 5 is not yet pinned. Closing that range was the cheapest unrun experiment in this whole chain.
It ran on 28 October, and half of that range closes. E70's ladder gives the B side a law — — and measures the operand carry-over this page had to choose between 1.01 and 1.57 at , which pins the 6% that choice was worth to roughly ±1.5–2%. The A side does not get a law: the same saturating form is rejected there, so the bottom-up burst range narrows but does not close, and the A side's shape is now an open question rather than a missing experiment. One claim E70 first made is withdrawn: its fitted asymptote is the curve's curvature, not a cap on operand-driven switching, because the experiment's own top rungs and both random-operand steps exceed it. No ceiling goes into this chain.
The coda, and the camera. Step 3's camera route reads heat at the back of the board, not at the die, and 28 October measured the path between them. It is a . So the camera's 0.05 Hz transfer is only 0.1953 of the steady-state response, and any absolute figure in millikelvin per watt has to say which steady gain it means: . The 17% between those two is itself a finding, and the fitted family is strained in two places at once. For the die's own thermal path the camera is the wrong instrument by two to five orders of magnitude — 0.25 ms vertically and 11 ms laterally, against a 0.05–0.15 Hz lock-in — so a further camera frequency can only pin down the board's pole count, which is what this one did.
5. What is still open
In the order that closing them would most change the picture. Updated 28 October 2026: every item below carries its new status — closed, narrowed, or still open — and the last block names what is newly open, including three things that are open because an experiment ran.
The knob test: move the cap and see whether the gap moves with it
Everything in §1 and §2 said the governor's power cap causes the speed gap, read from the governor's own log: strong evidence, but observational. The cap has now been moved — on aifoundry2 card 0, with the owner's authorization, under the firmware field manual's gates, in 11.4 card-minutes across five sessions with 39 set-and-restore commands, every one read back. The extrapolated 35–85 W table holds: . All-ones operands, which throw no power step at the card's own cap, throttle to , and the cause is separately switchable — at a 50 W cap the clock stays at . The sustained clamp turns out to be the thermal threshold: .
Still open. Three of six registered rules failed as written; both sustained random cells aborted on an 85 W board bound and were not retried, so nothing is known about random data under a raised threshold; the lowered-threshold cell never reached equilibrium inside its 76 s; and the registered drift check against the four-day-old baseline failed by 25.5 MHz and 2.5 W at identical settings, which looks like a thermal-path change and bounds every cross-session comparison. E69's data and change record
The temperature term the governor's power curve was missing
§4's one quantitative miss — all-ones operands sustained, predicted 775 MHz against a measured 738 — is a missing temperature term in the static power, and a desk model (E64-T1) now supplies one. It takes that miss , a factor of two to five. It is not a closure. The model's voltage exponent and its thermal trip are jointly unidentified: the miss crosses zero at two of eight labelled pairings, is still +18.5 MHz at the least-assumption corner, and the lowest error in the whole surface is not the pairing the model's own first write-up published. The fp16 all-ones cell never closes at any pairing. The sustained zeros-to-random ratio is still a clamp — the term narrows its window but every candidate cap stays inside it, so that prediction remains ordinal. E64-T1
The saturation ladder: how many bits, rather than which bits
The single-bit price list over-predicts a whole random word by about two, and the record did not separate the two candidate causes. It ran, on aifoundry3, 34.7 card-minutes, 203 of 203 runs through every gate. The answer is — the same number of flipped bits in two layouts cost different amounts, which no law in “how many” can produce. On the B side one saturating curve in the additive sum then fits fifteen rungs to , so the price list is usable as the bridge between the card and the netlist there, which it was not before. The operand carry-over is measured at , replacing a choice this page had to make.
The A side is not closed, and is newly open. Its multi-bit ladder was measured, but the same saturating form is rejected there: the fitted asymptote lies 28.6 standard errors below the ladder's own top rung, the fit's error is 4.7× the B side's, and the increments accelerate where saturation requires decay. So E70 measured the A-side ladder and did not find the law that describes it. One of its eight registered rules failed, and one headline claim is withdrawn — the fitted asymptote is a curvature, not a cap. E70
The leakage slope, which is the largest uncertainty in every per-bit price
Each run's power is corrected for the die temperature it ran at, using a leakage slope. The registered estimator fits that slope inside each run's own two-second window, while the kernel is running, so it reads a busy transient rather than idle leakage — and it returned 1.508 W/°C. An overnight idle heat-and-cool cycle measured this card's real idle leakage directly at , five times smaller, in agreement with three other estimates. Every price on this page is therefore published as a band. Re-running the reduction with the measured slope — as a labelled sensitivity, not as a replacement for the registered scoring — is a morning's desk work.
Done, for both cards and in the band each experiment ran in. E66 measured one card's idle slope; E71 measured the other's, on the card the 32-position price lists ran on and over the temperature band they launched in: . Every reduction on both cards has now been re-run at its own card's measured slope as a labelled sensitivity. The prices are cheaper: . The registered 1.508 W/°C estimator is 4–5× every measured idle slope and stays refuted.
What it taught, which is the part to carry: a leakage slope is not a card constant. It rises with die temperature — about 0.009 W/°C per °C on one card, 0.011 on the other over 51–65 °C — so about of the gap between the two cards' published figures is the temperature band, not the card, and a slope quoted without its band is ambiguous at the 20–30% level: larger than the 10% card-to-card difference it is usually invoked for. One registered rule of the re-pricing failed and is reported as failed: of 166 re-priced positions 164 fall, one does not move, and one rises 4.0% because its measurement window ran 0.09 °C cooler than its own zero's. No published verdict flips — 0 of 16. E71 · the re-reductions
The three things that keep the bottom-up count a floor
Detailed routing had never closed in the open flow, so there was no extracted parasitic file, no coupling capacitance and no measured glitch factor; half the design's capacitance was created after the point the gate-level simulation saw; and the A side had no multi-bit ladder.
Routing closes on both netlists, 0 DRC violations, 193 s each, with 251,162 coupling capacitors extracted — and it moved the count the wrong way, because the estimate it replaced was never coupling-free. The glitch factor is measured: , the largest single step any of these measurements has made. The capacitance is priced in full, and 43 of the 49.5 percentage points turned out to carry no switching energy at all. The A-side ladder ran and pinned the carry-over, so the 6% choice is gone — but its shape is open, as above. What keeps the count a floor now is one thing, narrower: the transport netlist in §3 has no detailed route, no glitch measurement and 37% of its capacitance priced, exactly the three axes the arithmetic netlist has cleared. the routed netlist · the glitch factor · the capacitance
Memory, and the instructions that trap
No flip ladder had run against a memory path. A DRAM tensor load costs 94–134 pJ per byte against a multiply-add's 5.8 pJ, so for most real work this chain prices the small half. And thirteen instructions — divide, square root, reciprocal square root, sine, the integer divides — trap in user mode, with no energy figure at all, although they are the normalisation half of a real kernel.
The trap half is answered, and the answer is structural
rather than thirteen energies. There is no emulation path in the firmware: a user-mode illegal
instruction is delegated and the exception handler ends that hart's kernel, 758 instructions counted on the
installed build. So the thirteen have no per-instruction energy, and what they cost is what their software
substitutes cost — a C float divide is safe (libgcc's own routine contains no trapping instruction, 299
instructions, 310–570 multiply-adds), while sqrtf is fatal, because libm's version contains
one. E76 then confirmed it on silicon: .
The memory half is measured, and the two ends of the hierarchy answer differently. E75 ran the first flip ladder on four memory paths, on two arms at once: the number of bits that change between consecutive words, and the number of ones each word carries. Per changed bit, . Per carried one, — so the L1 path pays for transitions and the DRAM path pays for ones, by a wide margin: . Two of the four changed-bit prices are bounds and not coefficients, because their ladders are not monotone — the middle rung reads below the bottom one in every pass, so the whole positive slope rests on the top rung. What it changes is what this page's own 94–134 pJ per byte means. The zeros-to-random chord that was the only handle before is reproduced and then explained only at one end: . So a bit-counting energy model is complete on the on-chip path and two thirds incomplete off it, the missing part being a property of the pattern rather than of its counts; and anyone saving DRAM energy by reducing transitions is working on the small term, while packing zeros is the lever.
All three are folded in, and none of them is a new row in §3. . The reasons are different, and worth separating. E74's bound is on the register-file cells' own stored bits — part of what §3's transport row already models, so counting it again would double-count; and at it is a ceiling worth having, because it says this term cannot be the explanation for what is left. E75 prices a memory path and not a multiply-add, so the arithmetic waterfall is untouched by design. E76's thirteen have no energy at all. What the three move is this list and the Levels tab, not the ledger.
What failed, and what is still open. E74's board ladder does not resolve the cell at all: resolving it would take about forty passes of the board meter, or a re-registration with the rail as the estimator. On E74, ; and . On E75, . On E76, ; and . Newly open from this block: whether a two-value alternating image is compressible on the DRAM link in a way random data is not, which is what the unexplained two thirds of that chord points at, and it needs its own experiment. E74 · E75 · E76
What the 28 October pass opened
Three of these are open because an experiment ran, which is the useful kind.
- The A side's shape
- Its multi-bit ladder is measured and the saturating form that fits the B side is rejected on it — asymptote 28.6 standard errors below its own top rung, increments accelerating. It needs a form that can be convex in the middle, and more rungs where the acceleration happens.
- The voltage exponent
- . What is settled is that the rival reading — the price scaling with the clock as well — is excluded everywhere at . Separating the physics from the estimator needs a rail-side idle leakage measurement, which exists for no card.
- The remaining unaccounted share
- , and the honest reading is that it is larger than that by whatever the transport's register-file model over-prices — a model the card's own zeros measurement already contradicts. E74 measured that array's storage cells on 28 October and bounded them at , which is the small part of it: what over-prices is the ports, the read mux tree and the clocking, and measuring those is the single most valuable thing left in §3.
- The DRAM path's pattern
- The heat path's model
- One pole alone is excluded and both pre-registered rivals are refuted, but the preferred family is strained in two places at once and whether the extra second of lag is transport or a second short pole is undecided. Settling it needs a lock-in frequency below 0.01 Hz.
- What the reviewers left open
- Every result above was checked by an independent adversarial pass, and the corrections are in the same data directories as the originals — including four claims withdrawn outright (a ceiling on operand-driven switching, a “few per cent” of the board on no meter, a closure of the result path, and a 95% figure that tracked whichever fitted value was chosen). Two process items stay open rather than fixed: no independent reviewer saw either card run, only the record and the data afterwards; and a leakage slope measured on a transient cooling cannot see the board parts the die sensor does not — a shared systematic that neither card's measurement bounds.
6. Sources and method
Every number on this page, and where it comes from
| Step | Experiment or model | Where |
|---|
Steps 6 to 8 rest on an open stand-in: the same RTL, built with a public cell library, because this chip’s own netlist is not public. A private archive cross-check of the same multiply-add was run on 26 October 2026 and again on against the same quantities;
Each experiment on a card was pre-registered by commit before the first launch, claimed in the lab's channel while it held the card, and scored against the rules it registered. Where a later pass found an error, the correction is in the same data directory as the original and the original is not quietly replaced.
Conventions, and the two places it is easy to go wrong
A rise is not a toggle. A capacitance C takes C·V² from the rail when its net rises and nothing when it falls, so a toggle — the per-edge average — costs ½C·V². Every single-edge figure on this page is per rise; per-toggle figures are half of it and are labelled where they appear. A table that mixes the two is out by exactly a factor of two, which is large enough to matter and small enough to miss.
An electron count from a board figure is a convention. Board power is not delivered at the die's rail, so dividing a board energy by 0.517 V gives a number of electrons that is useful for comparison and is not a count of anything. Every electron figure here uses the same 0.517 V; the cards that produced these measurements ran at 521.9 mV, so a count at their own rail would be 0.9% lower.
Temperature. Every SPICE number is at the kit's 25 °C corner. The die temperature enters only at Landauer's floor, where it is stated.
Built from the repository's own committed data directories. The chain in §2, the ledger and waterfall in §3 and the predictions in §4 are read at build time from the JSON a scored experiment wrote, so they cannot drift from the record. The 28 October additions from the Q129 lanes — in §§1, 4 and 5, and the measured terms quoted beside the ledger — are transcribed from the README or summary of the data directory named on each line, because several of those lanes publish the figure only in prose; a sample of them — — is re-checked against those directories' own JSON on every build, and the build fails if one does not match. Three of those lanes are not transcribed at all: , read from their reduction JSON the way §3's waterfall is.